
Obj/FWlib_apt32f172_tc1_gtc.o:     file format elf32-csky-little


Disassembly of section .text:

00000000 <GTC_ControlSet_Configure.part.0>:
/*************************************************************/  
void GTC_ControlSet_Configure (GTC_ControlSet_TypeDef GTC_ControlSet_x , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
	{
		GTC->CSR |= GTC_ControlSet_x;
   0:	1066      	lrw      	r3, 0	// 18 <GTC_ControlSet_Configure.part.0+0x18>
		if(GTC_ControlSet_x)
   2:	3840      	cmpnei      	r0, 0
		GTC->CSR |= GTC_ControlSet_x;
   4:	9340      	ld.w      	r2, (r3, 0)
   6:	9264      	ld.w      	r3, (r2, 0x10)
   8:	6cc0      	or      	r3, r0
   a:	b264      	st.w      	r3, (r2, 0x10)
		if(GTC_ControlSet_x)
   c:	0c05      	bf      	0x16	// 16 <GTC_ControlSet_Configure.part.0+0x16>
		{
			while(!(GTC->SR&GTC_ControlSet_x));
   e:	9266      	ld.w      	r3, (r2, 0x18)
  10:	68c0      	and      	r3, r0
  12:	3b40      	cmpnei      	r3, 0
  14:	0ffd      	bf      	0xe	// e <GTC_ControlSet_Configure.part.0+0xe>
	else
	{
		GTC->CCR |= GTC_ControlSet_x;
		while(GTC->SR&GTC_ControlSet_x);
	}
}
  16:	783c      	rts
  18:	00000000 	.long	0x00000000

0000001c <GTC_RESET_VALUE>:
	GTC->IDR 	= GTC_IDR_RST;											/**< IDR reset value         */    
  1c:	1369      	lrw      	r3, 0	// 1c0 <GTC_IO_Init+0x8c>
  1e:	134a      	lrw      	r2, 0x11000a	// 1c4 <GTC_IO_Init+0x90>
  20:	9360      	ld.w      	r3, (r3, 0)
  22:	b340      	st.w      	r2, (r3, 0)
	GTC->CSSR 	= GTC_CSSR_RST;	     								   	/**< CSSR reset value        */
  24:	3200      	movi      	r2, 0
  26:	b341      	st.w      	r2, (r3, 0x4)
	GTC->CEDR 	= GTC_CEDR_RST;  	 									/**< CEDR reset value        */
  28:	b342      	st.w      	r2, (r3, 0x8)
	GTC->SRR 	= GTC_SRR_RST;             								/**< SRR reset value         */
  2a:	b343      	st.w      	r2, (r3, 0xc)
	GTC->CSR 	= GTC_CSR_RST;             	 							/**< CSR reset value         */
  2c:	b344      	st.w      	r2, (r3, 0x10)
	GTC->CCR 	= GTC_CCR_RST;              							/**< CCR reset value         */
  2e:	b345      	st.w      	r2, (r3, 0x14)
	GTC->SR 	= GTC_SR_RST;           								/**< SR reset value          */
  30:	3202      	movi      	r2, 2
  32:	b346      	st.w      	r2, (r3, 0x18)
	GTC->IMSCR 	= GTC_IMSCR_RST;        								/**< IMSCR reset value       */
  34:	3200      	movi      	r2, 0
  36:	b347      	st.w      	r2, (r3, 0x1c)
	GTC->RISR	= GTC_RISR_RST;          								/**< RISR reset value        */
  38:	b348      	st.w      	r2, (r3, 0x20)
	GTC->MISR 	= GTC_MISR_RST;         								/**< MIS reset value        */
  3a:	b349      	st.w      	r2, (r3, 0x24)
	GTC->ICR 	= GTC_ICR_RST;          								/**< ICR reset value         */
  3c:	b34a      	st.w      	r2, (r3, 0x28)
	GTC->CDR 	= GTC_CDR_RST;        									/**< SR reset value          */
  3e:	b34b      	st.w      	r2, (r3, 0x2c)
	GTC->CSMR 	= GTC_CSMR_RST;           								/**< SR reset value          */
  40:	321f      	movi      	r2, 31
  42:	b34c      	st.w      	r2, (r3, 0x30)
	GTC->PRDR 	= GTC_PRDR_RST;           								/**< DR reset value          */
  44:	3200      	movi      	r2, 0
  46:	b34d      	st.w      	r2, (r3, 0x34)
	GTC->PULR	= GTC_PULR_RST;          								/**< SR reset value          */
  48:	b34e      	st.w      	r2, (r3, 0x38)
	GTC->CUCR 	= GTC_CUCR_RST;         								/**< SR reset value          */
  4a:	b353      	st.w      	r2, (r3, 0x4c)
	GTC->CDCR 	= GTC_CDCR_RST;            								/**< SR reset value          */
  4c:	b354      	st.w      	r2, (r3, 0x50)
	GTC->CVR	= GTC_CVR_RST;											/**< CVR reset value         */
  4e:	b355      	st.w      	r2, (r3, 0x54)
}
  50:	783c      	rts

00000052 <GTC_Configure>:
{
  52:	14c3      	push      	r4-r6
  54:	9883      	ld.w      	r4, (sp, 0xc)
  56:	6d53      	mov      	r5, r4
  58:	9884      	ld.w      	r4, (sp, 0x10)
  5a:	6d93      	mov      	r6, r4
	GTC->CSSR = GTC_FIN_X;													//selected GTC clk
  5c:	1299      	lrw      	r4, 0	// 1c0 <GTC_IO_Init+0x8c>
	GTC->CDR = GTC_DIVN|(GTC_DINM<<4);										//DIVN and DINM set
  5e:	4244      	lsli      	r2, r2, 4
	GTC->CSSR = GTC_FIN_X;													//selected GTC clk
  60:	9480      	ld.w      	r4, (r4, 0)
  62:	b401      	st.w      	r0, (r4, 0x4)
	GTC->CDR = GTC_DIVN|(GTC_DINM<<4);										//DIVN and DINM set
  64:	6c48      	or      	r1, r2
	GTC->CEDR = GTC_CLKEN|GTC_DBGEN;										//ENABLE GTC CLK
  66:	1219      	lrw      	r0, 0x80000001	// 1c8 <GTC_IO_Init+0x94>
  68:	b402      	st.w      	r0, (r4, 0x8)
	GTC->CDR = GTC_DIVN|(GTC_DINM<<4);										//DIVN and DINM set
  6a:	b42b      	st.w      	r1, (r4, 0x2c)
	GTC->CSMR = Counter_Size_X;												//selected GTC conter size
  6c:	b46c      	st.w      	r3, (r4, 0x30)
	GTC->PRDR = loadCounter_PRDR;											//Period of GTC date register
  6e:	b4ad      	st.w      	r5, (r4, 0x34)
	GTC->PULR = loadCounter_PULR;											//Pulse of GTC date register
  70:	b4ce      	st.w      	r6, (r4, 0x38)
}
  72:	1483      	pop      	r4-r6

00000074 <GTC_ControlSet_Configure>:
{
  74:	14d0      	push      	r15
	if (NewState != DISABLE)
  76:	3940      	cmpnei      	r1, 0
  78:	0c04      	bf      	0x80	// 80 <GTC_ControlSet_Configure+0xc>
  7a:	e0000000 	bsr      	0	// 0 <GTC_ControlSet_Configure.part.0>
}
  7e:	1490      	pop      	r15
		GTC->CCR |= GTC_ControlSet_x;
  80:	1270      	lrw      	r3, 0	// 1c0 <GTC_IO_Init+0x8c>
  82:	9340      	ld.w      	r2, (r3, 0)
  84:	9265      	ld.w      	r3, (r2, 0x14)
  86:	6cc0      	or      	r3, r0
  88:	b265      	st.w      	r3, (r2, 0x14)
		while(GTC->SR&GTC_ControlSet_x);
  8a:	9266      	ld.w      	r3, (r2, 0x18)
  8c:	68c0      	and      	r3, r0
  8e:	3b40      	cmpnei      	r3, 0
  90:	0bfd      	bt      	0x8a	// 8a <GTC_ControlSet_Configure+0x16>
  92:	07f6      	br      	0x7e	// 7e <GTC_ControlSet_Configure+0xa>

00000094 <GTC_ConfigInterrupt_CMD>:
//NewState:ENABLE,DISABLE
//ReturnValue:NONE
/*************************************************************/ 
void GTC_ConfigInterrupt_CMD(GTC_IMSCR_TypeDef GTC_IMSCR_X , FunctionalStatus NewState)
{
	if (NewState != DISABLE)
  94:	3940      	cmpnei      	r1, 0
  96:	126b      	lrw      	r3, 0	// 1c0 <GTC_IO_Init+0x8c>
  98:	0c06      	bf      	0xa4	// a4 <GTC_ConfigInterrupt_CMD+0x10>
	{
		GTC->IMSCR  |= GTC_IMSCR_X;						//SET
  9a:	9340      	ld.w      	r2, (r3, 0)
  9c:	9267      	ld.w      	r3, (r2, 0x1c)
  9e:	6c0c      	or      	r0, r3
  a0:	b207      	st.w      	r0, (r2, 0x1c)
	}
	else
	{
		GTC->IMSCR  &= ~GTC_IMSCR_X;					//CLR
	}
}
  a2:	783c      	rts
		GTC->IMSCR  &= ~GTC_IMSCR_X;					//CLR
  a4:	9360      	ld.w      	r3, (r3, 0)
  a6:	9347      	ld.w      	r2, (r3, 0x1c)
  a8:	6c02      	nor      	r0, r0
  aa:	6808      	and      	r0, r2
  ac:	b307      	st.w      	r0, (r3, 0x1c)
}
  ae:	07fa      	br      	0xa2	// a2 <GTC_ConfigInterrupt_CMD+0xe>

000000b0 <GTC_SoftwareReset>:
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_SoftwareReset(void)
{
	GTC->SRR = GTC_SWRST;							// Software reset
  b0:	1264      	lrw      	r3, 0	// 1c0 <GTC_IO_Init+0x8c>
  b2:	3201      	movi      	r2, 1
  b4:	9360      	ld.w      	r3, (r3, 0)
  b6:	b343      	st.w      	r2, (r3, 0xc)
}
  b8:	783c      	rts

000000ba <GTC_Start>:
//gtc start
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_Start(void)
{
  ba:	14d0      	push      	r15
  bc:	3001      	movi      	r0, 1
  be:	e0000000 	bsr      	0	// 0 <GTC_ControlSet_Configure.part.0>
	GTC_ControlSet_Configure (GTC_ControlSet_start_stop , ENABLE); 
}
  c2:	1490      	pop      	r15

000000c4 <GTC_start_stop>:
  c4:	14d0      	push      	r15
  c6:	e0000000 	bsr      	0	// ba <GTC_Start>
  ca:	1490      	pop      	r15

000000cc <GTC_Stop>:
//gtc stop
//EntryParameter:
//ReturnValue:NONE
/*************************************************************/ 
void GTC_Stop(void)
{
  cc:	14d0      	push      	r15
	GTC_ControlSet_Configure (GTC_ControlSet_start_stop , DISABLE); 
  ce:	3100      	movi      	r1, 0
  d0:	3001      	movi      	r0, 1
  d2:	e0000000 	bsr      	0	// 74 <GTC_ControlSet_Configure>
}
  d6:	1490      	pop      	r15

000000d8 <GTC_Set_Period>:
//gtc counter period DATA read 
//EntryParameter:loadCounter_PRDR,loadCounter_PULR
//ReturnValue:Conter prdr register value
/*************************************************************/  
void GTC_Set_Period(U32_T loadCounter_PRDR , U32_T loadCounter_PULR)
{
  d8:	14c1      	push      	r4
	GTC->CSR = (GTC->CSR & 0xFFFFFFFD) | 0x02;
  da:	117a      	lrw      	r3, 0	// 1c0 <GTC_IO_Init+0x8c>
	while(!((GTC->SR & 0x02)==0X02));
  dc:	3402      	movi      	r4, 2
	GTC->CSR = (GTC->CSR & 0xFFFFFFFD) | 0x02;
  de:	9360      	ld.w      	r3, (r3, 0)
  e0:	9344      	ld.w      	r2, (r3, 0x10)
  e2:	3aa1      	bseti      	r2, r2, 1
  e4:	b344      	st.w      	r2, (r3, 0x10)
	while(!((GTC->SR & 0x02)==0X02));
  e6:	9346      	ld.w      	r2, (r3, 0x18)
  e8:	6890      	and      	r2, r4
  ea:	3a40      	cmpnei      	r2, 0
  ec:	0ffd      	bf      	0xe6	// e6 <GTC_Set_Period+0xe>
	GTC->PRDR = loadCounter_PRDR;											//Period of GTC date register
  ee:	b30d      	st.w      	r0, (r3, 0x34)
	GTC->PULR = loadCounter_PULR;											//Pulse of GTC date register
  f0:	b32e      	st.w      	r1, (r3, 0x38)
}
  f2:	1481      	pop      	r4

000000f4 <GTC_Int_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Int_Enable(void)
{
    INTC_ISER_WRITE(TC1_INT);    
  f4:	1176      	lrw      	r3, 0	// 1cc <GTC_IO_Init+0x98>
  f6:	3280      	movi      	r2, 128
  f8:	9360      	ld.w      	r3, (r3, 0)
  fa:	23ff      	addi      	r3, 256
  fc:	4243      	lsli      	r2, r2, 3
  fe:	b340      	st.w      	r2, (r3, 0)
}
 100:	783c      	rts

00000102 <GTC_Int_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Int_Disable(void)
{
    INTC_ICER_WRITE(TC1_INT);    
 102:	1173      	lrw      	r3, 0	// 1cc <GTC_IO_Init+0x98>
 104:	32c0      	movi      	r2, 192
 106:	9360      	ld.w      	r3, (r3, 0)
 108:	4241      	lsli      	r2, r2, 1
 10a:	60c8      	addu      	r3, r2
 10c:	3280      	movi      	r2, 128
 10e:	4243      	lsli      	r2, r2, 3
 110:	b340      	st.w      	r2, (r3, 0)
}
 112:	783c      	rts

00000114 <GTC_Wakeup_Enable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Wakeup_Enable(void)
{
    INTC_IWER_WRITE(TC1_INT);    
 114:	116e      	lrw      	r3, 0	// 1cc <GTC_IO_Init+0x98>
 116:	3280      	movi      	r2, 128
 118:	9360      	ld.w      	r3, (r3, 0)
 11a:	23ff      	addi      	r3, 256
 11c:	4243      	lsli      	r2, r2, 3
 11e:	b350      	st.w      	r2, (r3, 0x40)
}
 120:	783c      	rts

00000122 <GTC_Wakeup_Disable>:
//EntryParameter:NONE
//ReturnValue:NONE
/*************************************************************/
void GTC_Wakeup_Disable(void)
{
    INTC_IWDR_WRITE(TC1_INT);    
 122:	116b      	lrw      	r3, 0	// 1cc <GTC_IO_Init+0x98>
 124:	32e0      	movi      	r2, 224
 126:	9360      	ld.w      	r3, (r3, 0)
 128:	4241      	lsli      	r2, r2, 1
 12a:	60c8      	addu      	r3, r2
 12c:	3280      	movi      	r2, 128
 12e:	4243      	lsli      	r2, r2, 3
 130:	b340      	st.w      	r2, (r3, 0)
}
 132:	783c      	rts

00000134 <GTC_IO_Init>:
//GTC_IO_G;GTC_IO_TXOUT(0->PB0.00 ;1->PA0.06;2->PC0.02;3->PA0.15),GTC_IO_TCLK(0->PA0.0),GTC_IO_TCAPX(0->PA1.0;1->PA1.1)
//ReturnValue:NONE
/*************************************************************/
void GTC_IO_Init(GTC_IO_MODE_TypeDef  GTC_IO_MODE_X , U8_T GTC_IO_G )
{
	if(GTC_IO_MODE_X==GTC_IO_TXOUT)
 134:	3841      	cmpnei      	r0, 1
 136:	082c      	bt      	0x18e	// 18e <GTC_IO_Init+0x5a>
	{
		if(GTC_IO_G==0)
 138:	3940      	cmpnei      	r1, 0
 13a:	0809      	bt      	0x14c	// 14c <GTC_IO_Init+0x18>
		{
			GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000006;										//T1OUT(PB0.00->AF3)
 13c:	1165      	lrw      	r3, 0	// 1d0 <GTC_IO_Init+0x9c>
	}
	else if(GTC_IO_MODE_X==GTC_IO_TCAPX)
	{
		if(GTC_IO_G==0)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000006;										//TCAP1(PA1.0->AF3)
 13e:	9340      	ld.w      	r2, (r3, 0)
 140:	9260      	ld.w      	r3, (r2, 0)
 142:	310f      	movi      	r1, 15
 144:	68c5      	andn      	r3, r1
 146:	3ba1      	bseti      	r3, r3, 1
 148:	3ba2      	bseti      	r3, r3, 2
 14a:	042d      	br      	0x1a4	// 1a4 <GTC_IO_Init+0x70>
		else if(GTC_IO_G==1)
 14c:	3941      	cmpnei      	r1, 1
 14e:	080b      	bt      	0x164	// 164 <GTC_IO_Init+0x30>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XF0FFFFFF)|0x05000000;										//T1OUT(PA0.06->AF2)
 150:	1161      	lrw      	r3, 0	// 1d4 <GTC_IO_Init+0xa0>
 152:	32f0      	movi      	r2, 240
 154:	9320      	ld.w      	r1, (r3, 0)
 156:	9160      	ld.w      	r3, (r1, 0)
 158:	4254      	lsli      	r2, r2, 20
 15a:	68c9      	andn      	r3, r2
 15c:	3bb8      	bseti      	r3, r3, 24
 15e:	3bba      	bseti      	r3, r3, 26
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000500;										//T1OUT(PC0.02->AF2)
 160:	b160      	st.w      	r3, (r1, 0)
		else if(GTC_IO_G==1)
		{
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000040;										//TCAP1(PA1.1->AF1)
		}
	}
}
 162:	783c      	rts
		else if(GTC_IO_G==2)
 164:	3942      	cmpnei      	r1, 2
 166:	080a      	bt      	0x17a	// 17a <GTC_IO_Init+0x46>
			GPIOC0->CONLR=(GPIOC0->CONLR & 0XFFFFF0FF)|0x00000500;										//T1OUT(PC0.02->AF2)
 168:	107c      	lrw      	r3, 0	// 1d8 <GTC_IO_Init+0xa4>
 16a:	32f0      	movi      	r2, 240
 16c:	9320      	ld.w      	r1, (r3, 0)
 16e:	9160      	ld.w      	r3, (r1, 0)
 170:	4244      	lsli      	r2, r2, 4
 172:	68c9      	andn      	r3, r2
 174:	3ba8      	bseti      	r3, r3, 8
 176:	3baa      	bseti      	r3, r3, 10
 178:	07f4      	br      	0x160	// 160 <GTC_IO_Init+0x2c>
		else if(GTC_IO_G==3)
 17a:	3943      	cmpnei      	r1, 3
 17c:	0bf3      	bt      	0x162	// 162 <GTC_IO_Init+0x2e>
			GPIOA0->CONHR=(GPIOA0->CONHR & 0X0FFFFFFF)|0x40000000;										//T1OUT(PA0.15->AF1)
 17e:	1076      	lrw      	r3, 0	// 1d4 <GTC_IO_Init+0xa0>
 180:	9340      	ld.w      	r2, (r3, 0)
 182:	9261      	ld.w      	r3, (r2, 0x4)
 184:	4364      	lsli      	r3, r3, 4
 186:	4b64      	lsri      	r3, r3, 4
 188:	3bbe      	bseti      	r3, r3, 30
 18a:	b261      	st.w      	r3, (r2, 0x4)
 18c:	07eb      	br      	0x162	// 162 <GTC_IO_Init+0x2e>
	else if(GTC_IO_MODE_X==GTC_IO_TCLK)
 18e:	3842      	cmpnei      	r0, 2
 190:	080c      	bt      	0x1a8	// 1a8 <GTC_IO_Init+0x74>
		if(GTC_IO_G==0)
 192:	3940      	cmpnei      	r1, 0
 194:	0be7      	bt      	0x162	// 162 <GTC_IO_Init+0x2e>
			GPIOA0->CONLR=(GPIOA0->CONLR & 0XFFFFFFF0)|0x00000005;										//TCLK(PA0.0->AF2)
 196:	1070      	lrw      	r3, 0	// 1d4 <GTC_IO_Init+0xa0>
 198:	310f      	movi      	r1, 15
 19a:	9340      	ld.w      	r2, (r3, 0)
 19c:	9260      	ld.w      	r3, (r2, 0)
 19e:	68c5      	andn      	r3, r1
 1a0:	3ba0      	bseti      	r3, r3, 0
 1a2:	3ba2      	bseti      	r3, r3, 2
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000040;										//TCAP1(PA1.1->AF1)
 1a4:	b260      	st.w      	r3, (r2, 0)
}
 1a6:	07de      	br      	0x162	// 162 <GTC_IO_Init+0x2e>
	else if(GTC_IO_MODE_X==GTC_IO_TCAPX)
 1a8:	3843      	cmpnei      	r0, 3
 1aa:	0bdc      	bt      	0x162	// 162 <GTC_IO_Init+0x2e>
		if(GTC_IO_G==0)
 1ac:	3940      	cmpnei      	r1, 0
 1ae:	0803      	bt      	0x1b4	// 1b4 <GTC_IO_Init+0x80>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFFF0)|0x00000006;										//TCAP1(PA1.0->AF3)
 1b0:	106b      	lrw      	r3, 0	// 1dc <GTC_IO_Init+0xa8>
 1b2:	07c6      	br      	0x13e	// 13e <GTC_IO_Init+0xa>
		else if(GTC_IO_G==1)
 1b4:	3941      	cmpnei      	r1, 1
 1b6:	0bd6      	bt      	0x162	// 162 <GTC_IO_Init+0x2e>
			GPIOA1->CONLR=(GPIOA1->CONLR & 0XFFFFFF0F)|0x00000040;										//TCAP1(PA1.1->AF1)
 1b8:	1069      	lrw      	r3, 0	// 1dc <GTC_IO_Init+0xa8>
 1ba:	31f0      	movi      	r1, 240
 1bc:	0412      	br      	0x1e0	// 1e0 <GTC_IO_Init+0xac>
 1be:	0000      	bkpt
 1c0:	00000000 	.long	0x00000000
 1c4:	0011000a 	.long	0x0011000a
 1c8:	80000001 	.long	0x80000001
	...
 1e0:	9340      	ld.w      	r2, (r3, 0)
 1e2:	9260      	ld.w      	r3, (r2, 0)
 1e4:	68c5      	andn      	r3, r1
 1e6:	3ba6      	bseti      	r3, r3, 6
 1e8:	07de      	br      	0x1a4	// 1a4 <GTC_IO_Init+0x70>
